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74LV139D Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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2 / 12 page Philips Semiconductors Product specification 74LV139 Dual 2-to-4 line decoder/demultiplexer 2 1998 Apr 28 853–1922 19290 FEATURES • Wide operating voltage: 1.0 to 5.5 V • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Typical V OLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C • Typical V OHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Demultiplexing capability • Two independent 2-to-4 decoders • Multifunction capability • Active LOW mutually exclusive outputs • Output capability: standard • I CC category: MSI APPLICATIONS • Memory decoding or data-routing • Code conversion DESCRIPTION The 74LV139 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT139. The 74LV139 is a dual 2-to-4 line decoder/demultiplexer. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nAn to nYn, nE to nYn CL = 15 pF; VCC = 3.3 V 11 10 ns CI Input capacitance 3.5 pF CPD Power dissipation capacitance per multiplexer VCC = 3.3 V VI = GND to VCC1 42 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40 °C to +125°C 74LV139 N 74LV139 N SOT38-4 16-Pin Plastic SO –40 °C to +125°C 74LV139 D 74LV139 D SOT109-1 16-Pin Plastic SSOP Type II –40 °C to +125°C 74LV139 DB 74LV139 DB SOT338-1 16-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV139 PW 74LV139PW DH SOT403-1 PIN CONFIGURATION SV00530 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1E 1A0 1A1 1Y0 1Y1 1Y2 1Y3 GND VCC 2E 2A0 2A1 2Y0 2Y1 2Y2 2Y3 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 15 1E, 2E Enable inputs (active LOW) 2, 3 1A0, 1A1 Address inputs 4, 5, 6, 7 1Y0 to 1Y3 Outputs (active LOW) 8 GND Ground (0 V) 12, 11, 10, 9 2Y0 to 2Y3 Outputs (active LOW) 14, 13 2A0, 2A1 Address inputs 16 VCC Positive supply voltage |
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