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74LV153N Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV153N
Szczegółowy opis  Dual 4-input multiplexer
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV153N Arkusz danych(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV153
Dual 4-input multiplexer
2
1998 Apr 28
853–1921 19309
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Non-inverting outputs
Separate enable for each output
Common select inputs
Permits multiplexing from n lines to 1 line
Enable line provided for cascading (n lines to 1 line)
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV153 is a low-voltage CMOS device that is pin and function
compatible with 74HC/HCT153.
The 74LV153 is a dual 4-input multiplexer which selects 2 bits of
data from up to four sources selected by common data select inputs
(S0, S1). The two 4-input multiplexer circuits have individual active
LOW output enable inputs (1E, 2E) which can be used to strobe the
outputs independently. The outputs (1Y, 2Y) are forced LOW when
the corresponding output enable inputs are HIGH. The 74LV153 is
the logic implementation of a 2-pole, 4-position switch, where the
position of the switch, is determined by the logic levels applied to S0
and S1. The logic equations for the outputs are:
1Y=1E.(1l0.S1.S0+1l1.S1.S0+1l2.S1.S0+1l3.S1.S0)
2Y=2E.(2l0.S1.S0+2l1.S1.S0+2l2.S1.S0+2l3.S1.S0)
The 74LV153 can be used to move data to a common output bus
from a group of registers. The state of the select inputs would
determine the particular register from which the data came. An
alternative application is a function generator. The device can
generate two functions or three variables. This is useful for
implementing highly irregular random logic.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
1ln, 2ln to nY
Sn to nY
nE to nY
CL = 15 pF;
VCC = 3.3 V
14
14
10
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
VI = GND to VCC1
30
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV153 N
74LV153 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV153 D
74LV153 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV153 DB
74LV153 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV153 PW
74LV153PW DH
SOT403-1


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