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74LV154N Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV154N
Szczegółowy opis  4-to-16 line decoder/demultiplexer
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV154
4-to-16 line decoder/demultiplexer
2
1998 Apr 28
853–1939 19309
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
16-line demultiplexing capability
Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
2-input enable gate for strobing or expansion
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV154 is a low-voltage CMOS device and is pin and function
compatible with 74HC/HCT154.
The 74LV154 decoders accept four active HIGH binary address
inputs (A0 to A3) and provide 16 mutually exclusive active LOW
outputs(Y0 to Y15).
The 2-input enable inputs (E0, E1) can be used to strobe the
decoder to eliminate the normal decoding “glitches” on the outputs,
or it can be used for expansion of the decoder.
The enable input has two AND’ed inputs which must be LOW to
enable the outputs.
The 74LV154 can be used as a 1-to-16 demultiplexer by using one
of the enable inputs as the multiplexed data input.
When the other enable is LOW, the addressed output will follow the
state of the applied data.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An, En to Yn
CL = 15 pF;
VCC = 3.3 V
11
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
VI = GND to VCC1
60
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi +Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic DIL
–40
°C to +125°C
74LV154 N
74LV154 N
SOT101-1
24-Pin Plastic SO
–40
°C to +125°C
74LV154 D
74LV154 D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV154 DB
74LV154 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV154 PW
74LV154PW DH
SOT355-1
PIN CONFIGURATION
SV00544
1
2
3
4
5
6
7
8
9
10
11
12
Y 0
Y 1
Y 2
Y 3
Y 4
Y 5
Y 6
Y 7
Y 8
Y 9
Y 10
GND
V CC
A 0
A 1
A 2
A 3
E 1
E 0
Y 15
Y 14
Y 13
Y 12
Y 11
24
23
22
21
20
19
18
17
16
15
14
13
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 13,
14, 15, 16, 17
Y0 to Y15
Outputs (active LOW)
18, 19
E0, E1
Enable inputs (active LOW)
12
GND
Ground (0 V)
23, 22, 21, 20
A0 to A3
Address inputs
16
VCC
Positive supply voltage


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