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74LV4067D Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV4067D
Szczegółowy opis  16-channel analog multiplexer/demultiplexer
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV4067
16-channel analog multiplexer/demultiplexer
2
1998 Jun 23
853-1997 19618
FEATURES
Optimized for low voltage applications: 1.0 to 6.0 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Low typ “ON” resistance:
60
W at Vcc – GND = 4.5 V
90
W at Vcc – GND = 3.0 V
145
W at Vcc – GND = 2.0 V
Typical “break before make” built in
Output capability: non-standard
I
CC category: MSI
DESCRIPTION
The 74LV4067 is a low-voltage CMOS device and is pin and
function compatible with 74HC/HCT4067.
The 74LV4067 is an 16-channel analog multiplexer/demultiplexer with
four address inputs (So to S3), an active LOW enable input (E), sixteen
independent inputs/outputs (Y0 to Y15) and a common input/output (Z).
The 74LV4067 contains sixteen bidirectional analog switches, each with
one side connected to an independent input/output (Y0 to Y15) and the
other side connected to a common input/output (Z).
With E LOW, one of the sixteen switches is selected (low impedance
ON–state) by S0 to S3. All unselected switches are in the high
impedance OFF-state. With E HIGH, all switches are in the high
impedance OFF-state, independent of S0 to S3.
The analog inputs/outputs (Y0 to Y15, and Z) can swing between Vcc
as a positive limit and GND as a negative limit.
Vcc – GND may not exceed 6.0 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPZH/tPZL
Turn “ON” time
E to VOS
Sn to VOS
CL = 15 pF
RL = 1KW
VCC = 3.3 V
25
27
ns
tPHZ/tPLZ
Turn “OFF” time
E to VOS
Sn to VOS
25
27
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per switch
See Notes 1 and 2
29
pF
CS
Maximum switch capacitance
independent (Y) common (Z)
5
45
pF
NOTE:
1.
CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; CS = max. switch capacitance in pF; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
2.
The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic DIL
–40
°C to +125°C
74LV4067 N
74LV4067 N
SOT101-1
24-Pin Plastic SO
–40
°C to +125°C
74LV4067 D
74LV4067 D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV4067 DB
74LV4067 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV4067 PW
74LV4067PW DH
SOT355-1


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