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74LV164 Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV164
Szczegółowy opis  8-bit serial-in/parallel-out shift register
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV164 Arkusz danych(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV164
8-bit serial-in/parallel-out shift register
2
1998 May 07
853–1961 19349
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Typical V
OLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Gated serial data inputs
Asynchronous master reset
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (Dsa or Dsb); either input can be
used as an active HIGH enable for data entry through the other
input. Both inputs must be connected together or an unused input
must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q0, which is the logical AND of
the two data inputs (Dsa, Dsb) that existed one set-up time prior to
the rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
CP to Qn
MR to Qn
CL = 15pF
VCC = 3.3V
12
12
ns
fmax
Maximum clock frequency
78
MHz
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
VCC = 3.3V
Notes 1 and 2
40
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi )S (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°C to +125°C
74LV164 N
74LV164 N
SOT27-1
14-Pin Plastic SO
–40
°C to +125°C
74LV164 D
74LV164 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV164 DB
74LV164 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV164 PW
74LV164PW DH
SOT402-1


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