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74LV164N Arkusz danych(PDF) 7 Page - NXP Semiconductors |
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74LV164N Arkusz danych(HTML) 7 Page - NXP Semiconductors |
7 / 12 page Philips Semiconductors Product specification 74LV164 8-bit serial-in/parallel-out shift register 1998 May 07 7 AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. tPLH tPHL 1/fmax VOH Qn OUTPUT VI CP INPUT GND VOL VM VM tw SV00351 Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency Vi VOL VM tw trem tPHL VM Qn OUTPUT CP INPUT GND VOH MR INPUT Vi GND SV00352 VM Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagation delay and the master reset to clock (CP) removal time t su t su CP INPUT Dn INPUT Qn OUTPUT VM th VM VM th Vl GND Vl GND VOH VOL SV00353 Figure 3. Data set-up and hold times for the Dn inputs NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT PULSE GENERATOR RT Vl D.U.T. VO CL RL= 1k Vcc Test Circuit for Outputs DEFINITIONS VCC VI < 2.7V 2.7–3.6V VCC 2.7V TEST tPLH/tPHL ≥ 4.5 V VCC RL = Load resistor CL = Load capacitance includes jig and probe capacitiance 50pF RT = Termination resistance should be equal to ZOUT of pulse generators. SV00902 Figure 4. Load circuitry for switching times |
Podobny numer części - 74LV164N |
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Podobny opis - 74LV164N |
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