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74LV165N Arkusz danych(PDF) 8 Page - NXP Semiconductors

Numer części 74LV165N
Szczegółowy opis  8-bit parallel-in/serial-out shift register
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV165N Arkusz danych(HTML) 8 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07
8
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
SV00592
D7 INPUT
VM
VM
VM
Q7 OUTPUT
Q7 OUTPUT
VOL
VOL
GND
VOH
VOH
VI
tPLH
tPHL
tPHL
tPLH
Figure 3. Data input (Dn) to output (Q7 or Q7) propagation
delays when PL is LOW.
SV00595
VM
VM
CP, CE
INPUT
DS INPUT
CP, CE
INPUT
GND
GND
GND
VI
VI
VI
stable
VM
th
tsu (H)
tW
tsu (L)
tsu
th
th
see note
CE may change only from HIGH-to-LOW while CP is LOW. The shaded
areas indicate when the input is permitted to change for predictable output
performance.
Figure 4. Set-up and hold times from the serial data input (DS) to
the clock (CP) and the clock enable (CE) inputs, from the clock
enable input (CE) to the clock input (CP) and from the clock input
(CP) to the clock enable input (CE).
Note to Figure 4
CE may change only from HIGH-to-LOW while CP is LOW. The
shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00593
VM
VM
Dn INPUT
PL INPUT
GND
GND
VI
VI
tsu
tsu
tH
tH
Figure 5. Set-up and hold times from the data inputs (Dn)
to the parallel load input (PL).
TEST CIRCUIT
PULSE
GENERATOR
RT
Vl
D.U.T.
VO
CL
RL= 1k
Vcc
Test Circuit for Outputs
DEFINITIONS
VCC
VI
< 2.7V
2.7–3.6V
VCC
2.7V
TEST
tPLH/tPHL
≥ 4.5 V
VCC
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
50pF
RT = Termination resistance should be equal to ZOUT of pulse generators.
SV00902
Figure 6. Load circuitry for switching times.


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