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74LV174 Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV174
Szczegółowy opis  Hex D-type flip-flop with reset; positive-edge trigger
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV174
Hex D-type flip-flop with reset; positive edge-trigger
2
1998 May 20
853–1964 19422
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Typical V
OLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
set–up time prior to the LOW–to–HIGH clock transition, is
transferred to the corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently
of clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
CP to Qn
MR to Qn
CL = 15pF
VCC = 3.3V
16
13
ns
fmax
Maximum clock frequency
77
MHz
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per flip-flop
VCC = 3.3V
Notes 1 and 2
17
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi )S (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV174 N
74LV174 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV174 D
74LV174 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV174 DB
74LV174 DB
SOT338-1
16-Pin Plastic TSSOP
–40
°C to +125°C
74LV174 PW
74LV174PW DH
SOT403-1


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