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74LV163PWDH Arkusz danych(PDF) 9 Page - NXP Semiconductors |
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74LV163PWDH Arkusz danych(HTML) 9 Page - NXP Semiconductors |
9 / 14 page Philips Semiconductors Product specification 74LV163 Presettable synchronous 4-bit binary counter; synchronous reset 1998 Apr 30 9 AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. Qn, TC tW SV00576 VM CP INPUT OUTPUT VM tPLH tPHL 1/fmax VOL VOH GND VI Figure 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. SV00578 VM CET INPUT TC OUTPUT VM tPHL tPLH GND VI VOL VOH Figure 2. Input (CET) to output (TC) propagation delays and output transition times. SV00579 VM VM PE INPUT CP INPUT Dn INPUT VM th tsu tsu tsu tsu th th th GND GND GND VI VI VI The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 3. Set-up and hold times for input (Dn) and parallel enable input (PE). SV00584 VM MR INPUT CP INPUT VM th tsu tsu th GND GND VI VI The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 4. MR set-up and hold times. SV00580 VM CEP, CET INPUT CP INPUT VM th tsu tsu th GND GND VI VI The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 5. CEP and CET set-up and hold times. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR RT VI D.U.T. VO CL RL = 1KΩ VCC Test Circuit for switching times DEFINITIONS VCC VI < 2.7V VCC TEST tPLH/tPHL RT = Termination resistance should be equal to ZOUT of pulse generators. 50pF SV00901 RL = Load resistor CL = Load capacitance includes jig and probe capacitance 2.7–3.6V 2.7V Figure 6. Load circuitry for switching times. |
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