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74LV164PWDH Arkusz danych(PDF) 6 Page - NXP Semiconductors |
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74LV164PWDH Arkusz danych(HTML) 6 Page - NXP Semiconductors |
6 / 12 page Philips Semiconductors Product specification 74LV164 8-bit serial-in/parallel-out shift register 1998 May 07 6 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM CONDITION LIMITS –40 to +85 °C LIMITS –40 to +125 °C UNIT VCC(V) MIN TYP1 MAX MIN MAX 1.2 – 75 – – – Propagation delay 2.0 – 26 39 – 49 tPHL/tPLH Propagation delay CP to Qn Figure 1 2.7 – 19 29 – 36 ns CP to Qn 3.0 to 3.6 – 142 23 – 29 4.5 to 5.5 – 122 19 – 24 1.2 – 75 – – – Propagation delay 2.0 – 26 39 – 49 tPHL Propagation delay MR to Qn Figure 2 2.7 – 19 29 – 36 ns MR to Qn 3.0 to 3.6 – 142 23 – 29 4.5 to 5.5 – 122 19 – 24 2.0 34 9 – 41 – tW Clock pulse width Figure 1 2.7 25 6 – 30 – ns tW HIGH to LOW Figure 1 3.0 to 3.6 20 52 – 24 – ns 4.5 to 5.5 13 42 16 2.0 34 10 – 41 – tW Master reset pulse Figure 2 2.7 25 8 – 30 – ns tW width; LOW Figure 2 3.0 to 3.6 20 62 – 24 – ns 4.5 to 5.5 13 52 16 1.2 – 30 – – – Removal time 2.0 19 10 – 24 – trem Removal time MR to CP Figure 2 2.7 14 8 – 18 – ns MR to CP 3.0 to 3.6 11 62 – 14 – 4.5 to 5.5 8 52 10 1.2 – 15 – – – Set up time 2.0 22 5 – 26 – tsu Set-up time Dsa,Dsb to CP Figure 3 2.7 16 4 – 19 – ns Dsa, Dsb to CP 3.0 to 3.6 13 32 – 15 – 4.5 to 5.5 9 22 10 1.2 – –10 – – – Hold time 2.0 5 –3 – 5 – th Hold time Dsa,Dsb to CP Figure 3 2.7 5 –2 – 5 – ns Dsa, Dsb to CP 3.0 to 3.6 5 –22 – 5 – 4.5 to 5.5 5 –12 5 2.0 14 40 – 12 – f Maximum clock Figure 1 2.7 19 58 – 16 – MHz fmax pulse frequency Figure 1 3.0 to 3.6 24 702 – 20 – MHz 4.5 to 5.5 36 1002 30 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. |
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