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74LV165PW Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV165PW
Szczegółowy opis  8-bit parallel-in/serial-out shift register
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
2
1998 May 07
853–1915 19349
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Asynchronous 8-bit parallel load
Synchronous serial input
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV165 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT165.
The 74LV165 is an 8-bit parallel-load or serial-in shift register with
complementary serial outputs (Q7 and Q7) available from the last
stage. When the parallel load (PL) input is LOW, parallel data from the
D0 to D7 inputs are loaded into the register asynchronously. When PL
is HIGH, data enters the register serially at the DS input and shifts one
place to the right (Q0→Q1→Q2, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter expansion by
tying the Q7 output to the DS input of the succeeding stage.
The clock input is a gated-OR structure which allows one input to be
used as an active LOW clock enable (CE) input. The pin assignment
for the CP and CE inputs is arbitrary and can be reversed for layout
convenience. The LOW-to-HIGH transition of input CE should only
take place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL is activated.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
CE, CP to Q7, Q7
PL to Q7, Q7
D7 to Q7, Q7
CL = 15 pF;
VCC = 3.3 V
18
18
14
ns
fmax
Maximum clock frequency
78
MHz
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
VCC = 3.3 V
VI = GND to VCC1
35
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV165 N
74LV165 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV165 D
74LV165 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV165 DB
74LV165 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV165 PW
74LV165PW DH
SOT403-1
PIN CONFIGURATION
SV00585
1
2
3
4
5
6
PL
CP
D4
D5
D6
D7
V
CC
CE
D3
16
15
14
13
12
11
7
8
GND
DS
Q7
10
9
Q7
D2
D1
D0
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
PL
Asynchronous parallel load
input (active LOW)
2
CP
Clock input (LOW to
HIGH, edge-triggered)
7
Q7
Complementary output from
the last stage
8
GND
Ground (0 V)
9
Q7
Serial output from last stage
10
DS
Serial data input
11, 12, 13, 14, 3, 4, 5, 6
D0 to D7
Parallel data inputs
15
CE
Clock enable input
(active LOW)
16
VCC
Positive supply voltage


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