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74LV259D Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV259D
Szczegółowy opis  8-bit addressable latch
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV259D Arkusz danych(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV259
8-bit addressable latch
2
1998 May 20
853-1988 19420
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV259 is a low-voltage CMOS device and is pin and function
compatible with 74HC/HCT259.
The 74LV259 is a high-speed 8-bit addressable latch designed for
general purpose storage applications in digital systems. The
74LV259 is a multifunction device capable of storing single-line data
in eight addressable latches, and also 3-to-8 decoder and
demultiplexer, with active HIGH outputs (Q0 to Q7), functions are
available. The 74LV259 also incorporate an active LOW common
reset (MR) for resetting all latches, as well as an active LOW enable
input (LE). The 74LV259 has four modes of operation as shown in
the mode select table. In the addressable latch mode, data on the
data line (D) is written into the addressed latch. The addressed latch
will follow the data input with all non-addressed latches remaining in
their previous states. In the memory mode, all latches remain in their
previous states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the addressed output
follows the state of the D input with all other outputs in the LOW
state. In the reset mode all outputs are LOW and unaffected by the
address (A0 to A2) and date (D) input. When operating the 74LV259
as an addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this should only
be done while in the memory mode. The mode select table
summarizes the operations of the 74LV259.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
D, An to Qn
LE to Qn
MR to Qn
CL = 15 pF;
VCC = 3.3 V
17
16
14
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per latch
VI = GND to VCC1
19
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV259 N
74LV259 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV259 D
74LV259 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV259 DB
74LV259 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV259 PW
74LV259PW DH
SOT403-1


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