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74LV259PWDH Arkusz danych(PDF) 8 Page - NXP Semiconductors |
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74LV259PWDH Arkusz danych(HTML) 8 Page - NXP Semiconductors |
8 / 14 page Philips Semiconductors Product specification 74LV259 8-bit addressable latch 1998 May 20 8 AC WAVEFORMS (Continued) VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6V; VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V. VOL and VOH are the typical output voltage drop that occur with the output load. tsu SV01609 VM Dn INPUT VM th th tsu VM LE INPUT GND GND Qn OUTPUT VOH VOL VCC VCC Q = D Q = D The shaded areas indicate when the input is permitted to change for predictable output performance Figure 5. Data set-up and hold times for D input to LE input. SV01610 VM An INPUT ADDRESS STABLE GND GND VCC VCC LE INPUT VM tsu th The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 6. Address set-up and hold times for An inputs to LE input. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR RT VI D.U.T. VO CL VCC 1k Open GND S1 VCC VI < 2.7V VCC TEST S1 tPLH/tPHL Open 2.7V 2.7–3.6V 50pF 1k 2 * VCC SV00905 DEFINITIONS RT = Termination resistance should be equal to ZOUT of pulse generators. RL = Load resistor CL = Load capacitance includes jig and probe capacitance Figure 7. Load circuitry for switching times. |
Podobny numer części - 74LV259PWDH |
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Podobny opis - 74LV259PWDH |
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