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74LV374D Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74LV374D Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) 2 1997 Mar 20 FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between V CC = 2.7V and VCC = 3.6V • Typical V OLP (output ground bounce) t 0.8V @ VCC = 3.3V, Tamb = 25°C • Typical V OHV (output VOH undershoot) u 2V @ VCC = 3.3V, Tamb = 25°C • Common 3-State output enable input • Output capability: bus driver • I CC category: MSI DESCRIPTION The 74LV374 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT374. The 74LV374 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay CP to Qn CL = 15pF VCC = 3.3V 14 ns fmax Maximum clock frequency 77 MHz CI Input capacitance 3.5 pF CPD Power dissipation capacitance per flip-flop Notes 1 and 2 25 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi )S (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL –40 °C to +125°C 74LV374 N 74LV374 N SOT146-1 20-Pin Plastic SO –40 °C to +125°C 74LV374 D 74LV374 D SOT163-1 20-Pin Plastic SSOP Type II –40 °C to +125°C 74LV374 DB 74LV374 DB SOT339-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enable input (active-LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3-State flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data inputs 10 GND Ground (0V) 11 CP Clock input (LOW-to-HIGH, edge- triggered) 20 VCC Positive supply voltage FUNCTION TABLE OPERATING INPUTS INTERNAL OUTPUTS MODES OE CP Dn FLIP-FLOPS Q0 to Q7 Load and read register L L ↑ ↑ l h L H L H Load register and disable outputs H H ↑ ↑ l h L H Z Z H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = High impedance OFF-state ↑ = LOW–to–HIGH clock transition |
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