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74LV4051N Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV4051N
Szczegółowy opis  8-channel analog multiplexer/demultiplexer
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV4051
8-channel analog multiplexer/demultiplexer
2
1998 Jun 23
853-1998 19618
FEATURES
Optimized for low voltage applications: 1.0 to 6.0 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Low typ “ON” resistance:
60
W at Vcc – VEE = 4.5 V
90
W at Vcc – VEE = 3.0 V
145
W at Vcc – VEE = 2.0 V
Logic level translation: to enable 3 V logic to communicate with ± 3
V analog signals
Typical “break before make” built in
Output capability: non-standard
I
CC category: MSI
DESCRIPTION
The 74LV4051 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4051.
The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with
three digital select inputs (S0 to S2) an active LOW enable input (E),
eight independent inputs/outputs (Y0 to Y7) and a common
input/output (Z).
With E LOW, one of the eight switches is selected (low impedance
ON-state) by S0 to S2. With E HIGH, all switches are in the high
impedance OFF-state, independent of S0 to S2.
VCC and GND are the supply voltage pins for the digital control
inputs (S0 to S2, and E). The VCC to GND ranges are 1.0 to 6.0 V.
The analog inputs/outputs (Y0 to Y7 and Z) can swing between VCC
as a positive limit and VEE as a negative limit. VCC - VEE may not
exceed 6.0 V. For operation as a digital multiplexer/demultiplexer,
VEE is connected to GND (typically ground).
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPZH/tPZL
Turn “ON” time
E to VOS
Sn to VOS
CL = 15 pF
RL = 1KW
VCC = 3.3 V
23
22
ns
tPHZ/tPLZ
Turn “OFF” time
E to VOS
Sn to VOS
25
20
ns
CI
Input capacitance
3.5
CPD
Power dissipation capacitance per switch
See Notes 1 and 2
25
pF
CS
Maximum switch capacitance
independent (Y) common (Z)
5
25
F
NOTES:
1.
CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) ((CL + CS) × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; CS = maximum switch capacitance in pF;
VCC = supply voltage in V;
((CL +CS) × VCC2 × fo) = sum of the outputs.
2.
The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
Code
16-Pin Plastic DIL
–40
°C to +125°C
74LV4051 N
74LV4051 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV4051 D
74LV4051 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV4051 DB
74LV4051 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV4051 PW
74LV4051PW DH
SOT403-1
PIN CONFIGURATION
SV01702
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
GND
VCC
Y4
Y6
Z
Y7
Y5
E
VEE
Y2
Y1
Y0
Y3
S0
S1
S2
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
3
Z
Common input/output
6
E
Enable input (active LOW)
7
VEE
Negative supply voltage
8
GND
Ground (0 V)
11, 10, 9
S0 to S2
Select inputs
13, 14, 15, 12,
1, 5, 2, 4
Y0 to Y7
Independent inputs/outputs
16
VCC
Positive supply voltage


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