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74LV4052PW Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74LV4052PW Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 16 page Philips Semiconductors Product specification 74LV4052 Dual 4-channel analog multiplexer/demultiplexer 2 1998 Jun 23 853-1999 19618 FEATURES • Optimized for low voltage applications: 1.0 to 6.0 V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Low typ “ON” resistance: 60 W at Vcc – VEE = 4.5 V 90 W at Vcc – VEE = 3.0 V 145 W at Vcc – VEE = 2.0 V • Logic level translation: to enable 3 V logic to communicate with ± 3 V analog signals • Typical “break before make” built in • Analog/Digital multiplexing and demultiplexing • Signal gating • Output capability: non-standard • I CC category: MSI DESCRIPTION The 74LV4052 is a low-voltage CMOS device and is pin and function compatible with the 74HC/HCT4052. The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer with a common select logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logics include two digital select inputs (S0 and S1) and an active LOW enable input (E). With E LOW, one of the four switches is selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches are in the high impedance OFF-state, independent of S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (S0, S1 and E). The VCC to GND ranges are 1.0 to 6.0 V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPZH/tPZL Turn “ON” time E or VOS Sn CL = 15 pF RL = 1KW V 33 V 30 ns tPHZ/tPLZ Turn “OFF” time E or VOS Sn VCC = 3.3 V 22 ns CI Input capacitance 3.5 CPD Power dissipation capacitance per switch See Notes 1 and 2 57 pF CS Maximum switch capacitance independent (Y) common (Z) 5 12 F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) ((CL + CS) × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; CS = maximum switch capacitance in pF; VCC = supply voltage in V; ((CL +CS) × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA Code 16-Pin Plastic DIL –40 °C to +125°C 74LV4052 N 74LV4052 N SOT38-4 16-Pin Plastic SO –40 °C to +125°C 74LV4052 D 74LV4052 D SOT109-1 16-Pin Plastic SSOP Type II –40 °C to +125°C 74LV4052 DB 74LV4052 DB SOT338-1 16-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV4052 PW 74LV4052PW DH SOT403-1 PIN CONFIGURATION SV01697 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 GND VCC 2Y0 2Y2 2Z 2Y3 2Y1 E VEE 1Y2 1Y1 1Z 1Y0 1Y3 S0 S1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 5, 2, 4 2Y0, 2Y3 Independent inputs/outputs 6 E Enable input (active LOW) 7 VEE Negative supply voltage 8 GND Ground (0 V) 10, 9 S0, S1 Select inputs 12, 14, 15, 11 1Y0 to 1Y3 Independent inputs/outputs 13, 3 1Z, 2Z Common inputs/outputs 16 VCC Positive supply voltage |
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