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74LV4094 Arkusz danych(PDF) 4 Page - NXP Semiconductors |
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74LV4094 Arkusz danych(HTML) 4 Page - NXP Semiconductors |
4 / 14 page Philips Semiconductors Product specification 74LV4094 8-stage shift-and-store bus register 1998 Jun 23 4 FUNCTION TABLE INPUTS PARALLEL OUTPUT SERIAL OUTPUTS CP OE STR D QP0 QPn QS1 QS2 ↑ L X X Z Z Q’6 NC ↓ L X X Z Z NC QP7 ↑ H L X NC NC Q’6 NC ↑ H H L L QPn–1 Q’6 NC ↑ H H H H QPn–1 Q’6 NC ↓ H H H NC NC NC QP7 NOTES: H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state NC = no change ↑ = LOW-to–HIGH CP transition ↓ = HIGH-to-LOW CP transition Q’6 = the information in the 8th register stage is transferred to the 8th register stage and QSn clock edge. TIMING DIAGRAM SV01616 CP CLOCK INPUT DATA INPUT STROBE INPUT OUTPUT ENABLE INPUT INTERNAL Q’0 (FF0) OUTPUT INTERNAL Q’6 (FF6) OUTPUT Z–state Z–state SERIAL OUTPUT SERIAL OUTPUT D STR OE QP0 QP6 QS2 QS1 |
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