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74LV4053PWDH Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV4053PWDH
Szczegółowy opis  Triple 2-channel analog multiplexer/demultiplexer
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV4053PWDH Arkusz danych(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV4053
Triple 2-channel analog multiplexer/demultiplexer
2
853-2000 19618
1998 Jun 23
FEATURES
Optimized for low voltage applications: 1.0 to 6.0 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Low typ “ON” resistance:
100
W at Vcc – VEE = 4.5 V
150
W at Vcc – VEE = 3.0 V
240
W at Vcc – VEE = 2.0 V
Logic level translation: to enable 3 V logic to communicate with ± 3
V analog signals
Typical “break before make” built in
Output capability: non-standard
I
CC category: MSI
DESCRIPTION
The 74LV4053 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4053.
The 74LV4053 is a triple 2-channel analog multiplexer/demultiplexer with
a common enable input (E). Each multiplexer/demultiplexer has two
independent inputs/outputs (nY0 to nY1), a common input/output (nZ)
and three digital select inputs (S1 to S3).
With E LOW, one of the two switches is selected (low impedance
ON-state) by S1 to S3 With E HIGH, all switches are in the high
impedance OFF-states, independent of S1 and S3.
VCC and GND are the supply voltage pins for the digital control inputs
(S1, to S3, and E). The VCC to GND ranges are 1.0 to 6.0 V. The
analog inputs/outputs (nY0, to nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC - VEE may not
exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, VEE
is connected to GND (typically ground).
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPZH/tPZL
Turn “ON” time
E to VOS
Sn to VOS
CL = 15 pF
RL = 1KW
VCC = 3.3 V
16
20
ns
tPHZ/tPLZ
Turn “OFF” time
E to VOS
Sn to VOS
17
16
ns
CI
Input capacitance
3.5
CPD
Power dissipation capacitance per switch
See Notes 1 and 2
36
pF
CS
Maximum switch capacitance
independent (Y) common (Z)
5
8
F
NOTES:
1.
CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) ((CL + CS) × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; CS = maximum switch capacitance in pF;
VCC = supply voltage in V;
((CL +CS) × VCC2 × fo) = sum of the outputs.
2.
The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV4053 N
74LV4053 N
SOT38-1
16-Pin Plastic SO
–40
°C to +125°C
74LV4053 D
74LV4053 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV4053 DB
74LV4053 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV4053 PW
74LV4053PW DH
SOT403-1
PIN CONFIGURATION
SV01687
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
GND
VCC
2Y1
2Y0
3Y1
3Z
3Y0
E
VEE
2Z
1Z
1Y1
1Y0
S1
S2
S3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2, 1
2Y0, 2Y1
Independent inputs/outputs
5, 3
3Y0, 3Y1
Independent inputs/outputs
6
E
Enable input (active LOW)
7
VEE
Negative supply voltage
8
GND
Ground (0 V)
11, 10, 9
S1 to S3
Select inputs
12, 13
1Y0, 1Y1
Independent inputs/outputs
14, 15, 4
1Z to 3Z
Common inputs/outputs
16
VCC
Positive supply voltage


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