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74LV4094D Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74LV4094D Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 14 page Philips Semiconductors Product specification 74LV4094 8-stage shift-and-store bus register 1998 Jun 23 10 SV01618 outputs disabled outputs enabled outputs enabled tPHZ tPZH tPZL tPLZ VX VY VM VM VM OE INPUT OUTPUT HIGH-to-OFF OFF-to-HIGH OUTPUT LOW-to-OFF OFF-to-LOW GND VCC VCC VOL VOH GND Figure 3. 3-State enable and disable times for input OE. SV01617 VM CP INPUT D INPUT QPn, QS1, QS2 OUTPUT VM VM th th tsu tsu VCC VCC GND GND VOL VOH The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 4. Data set-up and hold times for the data input (D). TEST CIRCUIT VM VM tW NEGATIVE PULSE 10% 10% 90% 90% 0V VM VM tW VI POSITIVE PULSE 90% 90% 10% 10% 0V tTHL (tf) tTLH (tr)tTHL (tf) tTLH (tr) VM = 1.5V Input Pulse Definition SY00044 SWITCH POSITION PULSE GENERATOR RT Vl D.U.T. VO CL= 50pF RL = 1k Vcc Test Circuit for Outputs Open GND S1 VS1 DEFINITIONS VCC VI < 2.7V 2.7–3.6V VCC 2.7V TEST S1 tPLZ/tPZL tPLH/tPHL tPHZ/tPZH VS1 Open GND VS1 ≥ 4.5 V 2 < VCC VCC 2 < VCC RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VI 2 < VCC RL = 1k Figure 5. Load circuitry for switching times. |
Podobny numer części - 74LV4094D |
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Podobny opis - 74LV4094D |
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