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74LV423PW Arkusz danych(PDF) 4 Page - NXP Semiconductors |
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74LV423PW Arkusz danych(HTML) 4 Page - NXP Semiconductors |
4 / 16 page Philips Semiconductors Preliminary specification 74LV423 Dual retriggerable monostable multivibrator with reset 1997 Feb 04 4 LOGIC DIAGRAM R nREXT/CEXT VCC Q Q RD RR CL CL VCC CL CL CL A B SV00163 VCC It is recommended that Pin 6 (2CEXT) and Pin 14 (1CEXT) by externally grounded to Pin 8 (GND) FUNCTION TABLE INPUTS OUTPUTS nRD nA nB nQ nQ L X X L H X H X L * H * X X L L * H * H L ↑ H ↓ H NOTES: * If the monostable was triggered before this condition was established, the pulse will continue as programmed. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH transition ↓ = HIGH-to-LOW transition = one HIGH level output pulse = one LOW level output pulse VCC REXT CEXT to nCEXT (pin 14 or 6) to nREXT/CEXT (pin 15 or 7) SV00101 Figure 1. Timing Component Connection |
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