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74LV573PW Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV573PW
Szczegółowy opis  Octal D-type transparent latch 3-State
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV573PW Arkusz danych(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV573
Octal D-type transparent latch (3-State)
2
1998 Jun 10
853-1989 19545
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Typical V
OLP (output ground bounce) < 0.8V at VCC = 3.3V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) > 2V at VCC = 3.3V,
Tamb = 25°C
Inputs and outputs on opposite sides of package allowing easy
interface with microprocessors
Useful as input or output port for microprocessors/microcomputer
Common 3-State output enable input
Output capability: bus driver
I
CC category: MSI
DESCRIPTION
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘573’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin
arrangement.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
Dn to Qn
LE to Qn
CL = 15pF
VCC = 3.3V
12
13
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per latch
Notes 1, 2
26
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi ) (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°C to +125°C
74LV573 N
74LV573 N
SOT146-1
20-Pin Plastic SO
–40
°C to +125°C
74LV573 D
74LV573 D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV573 DB
74LV573 DB
SOT339-1
20-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV573 PW
74LV573PW DH
SOT360-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enabled input (active LOW)
2, 3, 4, 5,
6, 7, 8, 9
D0–D7
Data inputs
19, 18, 17, 16,
15, 14, 13, 12
Q0–Q7
Data outputs
10
GND
Ground (0V)
11
LE
Latch enable input (active HIGH)
20
VCC
Positive supply voltage


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