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74LV574DB Arkusz danych(PDF) 7 Page - NXP Semiconductors

Numer części 74LV574DB
Szczegółowy opis  Octal D-type flip-flop; positive edge-trigger 3-State
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV574DB Arkusz danych(HTML) 7 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV574
Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10
7
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V and v 3.6V
VM = 0.5 * VCC at VCC t 2.7V and w 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V and v 3.6V
VX = VOL + 0.1VCC at VCC < 2.7V and w 4.5V
VY = VOH – 0.3V at VCC w 2.7V and v 3.6V
VY = VOH – 0.1VCC at VCC < 2.7V and w 4.5V
SV00718
GND
VOL
VI
VOH
VM
CP INPUT
Qn OUTPUT
VM
tPLH
tPHL
1/fmax
tW
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse (CP) and the maximum clock pulse frequency
outputs
disabled
SV00344
VI
OE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
VM
tPLZ
tPHZ
tPZL
VY
outputs
enabled
outputs
enabled
VX
VM
tPZH
VM
Figure 2. 3-state enable and disable times
t
su
t
su
SV00345
CP INPUT
Dn INPUT
Qn OUTPUT
VM
th
VM
VM(1)
th
VI
GND
VI
GND
VOH
VOL
NOTE: the shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3.
Data set-up and hold times for the Dn input to the CP
input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
RL = 1k
VCC
Test Circuit for Outputs
DEFINITIONS
VCC
VI
< 2.7V
VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
2.7V
2.7–3.6V
w 4.5V
VCC
50 pF
SV00896
S1
tPLZ/tPZL
tPHZ/tPZH
Open
2 * VCC
GND
RL = 1k
Open
2 * VCC
GND
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance.
Figure 4.
Load circuitry for switching times


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