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74LV595D Arkusz danych(PDF) 9 Page - NXP Semiconductors |
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74LV595D Arkusz danych(HTML) 9 Page - NXP Semiconductors |
9 / 16 page Philips Semiconductors Product specification 74LV595 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 1998 Apr 20 9 AC WAVEFORMS VM = 1.5V at VCC w 2.7V VM = 0.5 * VCC at VCC t 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC ≥ 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH – 0.3V at VCCw 2.7V VY = VOH – 0.1VCC at VCC < 2.7V SV00718 GND VOL VI VOH VM CP INPUT Qn OUTPUT VM tPLH tPHL 1/fmax tW Figure 1. Clock (SHCP) to output (Q7’), propagation delays, the shift clock pulse width and the maximum shift clock frequency. SV00727 VM SHCP INPUT STCP INPUT Qn OUTPUT VM VM 1/fmax tsu tW tPHL tPLH VI VI GND GND VOL VOH Figure 2. Storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. outputs disabled SV00344 VI OE INPUT GND VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND VM tPLZ tPHZ tPZL VY outputs enabled outputs enabled VX VM tPZH VM Figure 3. 3-State enable and disable times for input OE. SV00722 t su t su SHCP INPUT DS INPUT Q7’ OUTPUT VM th VM VM th VI GND VI GND vOH VOL Figure 4. Data set-up and hold times for the data input (DS). |
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