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74LV595D Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74LV595D Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 16 page Philips Semiconductors Product specification 74LV595 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 1998 Apr 20 10 AC WAVEFORMS (Continued) VM = 1.5V at VCC w 2.7V VM = 0.5 * VCC at VCC t 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC ≥ 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH – 0.3V at VCCw 2.7V VY = VOH – 0.1VCC at VCC < 2.7V SV00728 VM MR INPUT SHCP INPUT Q7’ OUTPUT VM VM trem tW tPHL VI VI GND GND VOL VOH Figure 5. Master reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SHCP) removal time. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR RT VI D.U.T. VO CL VCC RL = 1k Test Circuit for switching times Open GND S1 DEFINITIONS VCC VI < 2.7V VCC TEST S1 tPLH/tPHL Open RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. 2 < VCC tPLZ/tPZL 2.7V 2.7–3.6V tPHZ/tPZH GND 50pF SV00895 RL = 1k 2 * VCC Figure 6. Load circuitry for switching times. |
Podobny numer części - 74LV595D |
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Podobny opis - 74LV595D |
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