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MC145170DT1 Arkusz danych(PDF) 10 Page - Motorola, Inc |
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MC145170DT1 Arkusz danych(HTML) 10 Page - Motorola, Inc |
10 / 27 page MC145170–1 MOTOROLA 10 This output can be enabled, disabled, and inverted via the C register. If desired, PDout can be forced to the high–impe– dance state by utilization of the disable feature in the C regis- ter (patented). φR and φV Double–Ended Phase/Frequency Detector Outputs (Pins 14, 15) These outputs can be combined externally to generate a loop error signal. Through use of a Motorola patented tech- nique, the detector’s dead zone has been eliminated. There- fore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/fre- quency detector is described below and is shown in Fig- ure 17. POL bit (C7) in the C register = low (see Figure 14) Frequency of fV > fR or Phase of fV Leading fR: φV = nega- tive pulses, φR = essentially high Frequency of fV < fR or Phase of fV Lagging fR: φV = essen- tially high, φR = negative pulses Frequency and Phase of fV = fR: φV and φR remain essen- tially high, except for a small minimum time period when both pulse low in phase POL bit (C7) = high Frequency of fV > fR or Phase of fV Leading fR: φR = nega- tive pulses, φV = essentially high Frequency of fV < fR or Phase of fV Lagging fR: φR = essen- tially high, φV = negative pulses Frequency and Phase of fV = fR: φV and φR remain essen- tially high, except for a small minimum time period when both pulse low in phase These outputs can be enabled, disabled, and inter- changed via the C register (patented). LD Lock Detector Output (Pin 11) This output is essentially at a high level with narrow low– going pulses when the loop is locked (fR and fV of the same phase and frequency). The output pulses low when fV and fR are out of phase or different frequencies (see Figure 17). This output can be enabled and disabled via the C register (patented). Upon power up, on–chip initialization circuitry disables LD to a static low logic level to prevent a false “lock” signal. If unused, LD should be disabled and left open. POWER SUPPLY VDD Most Positive Supply Potential (Pin 16) This pin may range from + 2.5 to 5.5 V with respect to VSS. For optimum performance, VDD should be bypassed to VSS using low–inductance capacitor(s) mounted very close to the device. Lead lengths on the capacitor(s) should be minimized. (The very fast switching speed of the device causes current spikes on the power leads.) VSS Most Negative Supply Potential (Pin 12) This pin is usually ground. For measurement purposes, the VSS pin is tied to a ground plane. ENB CLK Din POWER UP 1 2 3 4 5 1 2 3 4 NOTE: This initialization sequence must be used immediately after power up if control of the CLK pin is not possible. That is, if CLK (pin 7) toggles or floats upon power up, use the above sequence to reset the device. Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced to below 2.5 V, but not down to 0 V (for example, the supply drops down to 1 V). This is necessary because the on–chip power–on reset is only activated when the supply ramps up from 0 V. ZEROES DON’T CARES DON’T CARES ONE ZEROES ZERO Figure 13. Reset Sequence |
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