ST19NR66

4/5

Figure 1.

Block Diagram

Software development

Software development and firmware generation (ROM and options) are supported by a

comprehensive set of development tools, dedicated at development and validation of

software:

Revision history

INTERNAL BUS

MEMORY ACCESS FIREWALL

I/O

1 Serial

I/O

Inter-

face

GND

8 Bit

CPU

3 x 8

Bit

Timer

CRC

Module

CLK

Clock

Gene-

rator

Module

ST ROM, MAP and EDES FIREWALL

RAM

USER ROM

ST ROM, RF

and CRYPTO

LIBRARIES

EDES

ACCELE-

RATOR

MAP

529

Vcc

TRNG

Secu-

rity

Admin.

RESET

EEPROM

IART

RF

UART

RF

Inter-

face

AC0

AC1

Table 1.

Document revision history

Date

Revision

Changes

03-Nov-2005

1

Initial release.

14-Nov-2005

2

Speed values updated. See Speed on page 2 in table.

17-Jan-2006

3

Disclaimer updated.