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AD9212BCPZ-65 Arkusz danych(PDF) 6 Page - Analog Devices

Numer części AD9212BCPZ-65
Szczegółowy opis  Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9212BCPZ-65 Arkusz danych(HTML) 6 Page - Analog Devices

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AD9212
Rev. 0 | Page 6 of 56
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9212-40
AD9212-65
Parameter1
Temp
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK2
Maximum Clock Rate
Full
40
65
MSPS
Minimum Clock Rate
Full
10
10
MSPS
Clock Pulse Width High (tEH)
Full
12.5
7.7
ns
Clock Pulse Width Low (tEL)
Full
12.5
7.7
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
1.5
2.3
3.1
1.5
2.3
3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
300
ps
Fall Time (tF) (20% to 80%)
Full
300
300
ps
FCO Propagation Delay (tFCO)
Full
1.5
2.3
3.1
1.5
2.3
3.1
ns
DCO Propagation Delay (tCPD)4
Full
tFCO +
(tSAMPLE/20)
tFCO +
(tSAMPLE/20)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
ps
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Full
±50
±200
±50
±200
ps
Wake-Up Time (Standby)
25°C
600
600
ns
Wake-Up Time (Power-Down)
25°C
375
375
μs
Pipeline Latency
Full
8
8
CLK
cycles
APERTURE
Aperture Delay (tA)
25°C
750
750
ps
Aperture Uncertainty (Jitter)
25°C
<1
<1
ps rms
Out-of-Range Recovery Time
25°C
1
1
CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Can be adjusted via the SPI interface.
3 Measurements were made using a part soldered to FR4 material.
4 tSAMPLE/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.


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