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ADM1177-2ARMZ-R7 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADM1177-2ARMZ-R7 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 16 page ADM1177 Preliminary Technical Data Rev. PrD | Page 6 of 16 PIN CONFIGURATIONS 1 2 3 4 ADM1177 TOP VIEW (NOT TO SCALE) Vcc ADR SDA GATE ON TIMER SENSE SS GND 5 SCL 10 9 8 7 6 Figure 3. Pin Configurations PIN FUNCTIONAL DESCRIPTIONS Table 3. Pin No. Name Description 1 VCC Positive supply input pin. The operating supply voltage range is between 3.15 V to 14 V. An undervoltage lockout (UVLO) circuit resets the ADM1177 when a low supply voltage is detected. 2 SENSE Current sense input pin. A sense resistor between the VCC and SENSE pins sets the analog current limit. The hotswap operation of the ADM1177 controls the external FET gate to maintain the (VVCC-VSENSE) voltage at 100 mV or below. 3 ON Undervoltage input pin. Active high pin. An internal ON comparator has a trip threshold of 1.3 V and the output of this comparator is used as an enable for the hotswap operation. With an external resistor divider from VCC to GND, this pin can be used to enable the hotswap operation one a specific voltage on VCC, giving an undervoltage function. 4 GND Chip Ground Pin 5 TIMER Timer pin. An external capacitor CTIMER sets a 270 ms/µF initial timing cycle delay and a 21.7 ms/µF fault delay. The GATE pin turns off whenever the TIMER pin is pulled beyond the upper threshold. An overvoltage detection with an external zener can be used to force this pin high. 6 SCL I2C Clock Pin. Open-drain output requires an external resistive pull-up. 7 SDA I2C Data I/O Pin. Open-drain output requires an external resistive pull-up. 8 ADR I2C Address Pin. This pin can be tied low, tied high, left floating or tied low through a resistor to set four different I2C addresses. 9 SS Soft-Start Pin. This pin controls the reference on the current sense amplifier. A 10 µA current source charges this pin at startup. A capacitor on this pin will then set the slope of the initial current ramp. This pin can also be driven to a voltage to alter the reference directly, thereby adjusting the current limit level. 10 GATE GATE Output Pin. This pin is the high side gate drive of an external N-channel FET. This pin is driven by the FET drive controller which utilises a charge pump to provide a 12 µA pull-up current to charge the FET gate pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor) by modulating the GATE pin. |
Podobny numer części - ADM1177-2ARMZ-R7 |
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Podobny opis - ADM1177-2ARMZ-R7 |
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