FM20L08 - Extended Temp.
Rev. 1.4
Oct. 2005
Page 2 of 14
CE
Control
Logic
WE
A(16:3)
A(2:0)
I/O Latch & Bus Driver
OE
DQ(7:0)
16K x 8 block
16K x 8 block
16K x 8 block
16K x 8 block
16K x 8 block
16K x 8 block
16K x 8 block
16K x 8 block
VDD Monitor
VDD
LVL
A(16:0)
Write
Protect
Column Decoder
. . .
Figure 1. Block Diagram
Pin Description
Pin Name
Type
Pin Description
A(16:0)
Input
Address inputs: The 17 address lines select one of 131,072 bytes in the FRAM array.
The address value is latched on the falling edge of /CE. Addresses A(2:0) are used for
page mode read and write operations.
/CE
Input
Chip Enable inputs: The device is selected and a new memory access begins when /CE
is low. The entire address is latched internally on the falling edge of chip enable.
Subsequent changes to the A(2:0) address inputs allow page mode operation.
/WE
Input
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM20L08 to write the data on the DQ bus to the FRAM array. The falling edge of /WE
latches a new column address for fast page mode write cycles.
/OE
Input
Output Enable: When /OE is low, the FM20L08 drives the data bus when valid data is
available. Deasserting /OE high tri-states the DQ pins.
DQ(7:0)
I/O
Data: 8-bit bi-directional data bus for accessing the FRAM array.
/LVL
Output
Low Voltage Lockout: When the voltage monitor detects that VDD is below VTP, the
/LVL pin will be asserted low. While /LVL is low, the memory array cannot be accessed
which prevents a low voltage write from corrupting data. When VDD is within its normal
operating limits, the /LVL signal will be pulled high.
DNU
-
Do Not Use: This pin should be left unconnected.
VDD
Supply
Supply Voltage: 3.3V
VSS
Supply
Ground