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6 / 89 page 4 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A TA SH EE T Write Operation Status . . . . . . . . . . . . . . . . . . . . . 48 DQ7: Data# Polling ................................................................. 48 Figure 8. Data# Polling Algorithm ................................................... 48 DQ6: Toggle Bit I .................................................................... 49 Figure 9. Toggle Bit Algorithm......................................................... 50 DQ2: Toggle Bit II ................................................................... 50 Table 22. DQ6 and DQ2 Indications ...............................................51 Reading Toggle Bits DQ6/DQ2 .............................................. 51 DQ5: Exceeded Timing Limits ................................................ 51 DQ3: Sector Erase Timer ....................................................... 51 Table 23. Write Operation Status ....................................................52 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 53 Figure 10. Maximum Negative Overshoot Waveform ..................... 53 Figure 11. Maximum Positive Overshoot Waveform....................... 53 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 53 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 54 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 12. Test Setup...................................................................... 55 Table 24. Test Specifications ..........................................................55 Key to Switching Waveforms . . . . . . . . . . . . . . . 55 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 55 Figure 13. Input Waveforms and Measurement Levels .................. 55 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56 VCC Power-up ......................................................................... 56 Figure 14. VCC Power-up Diagram ................................................. 56 CLK Characterization ............................................................. 56 Figure 15. CLK Characterization..................................................... 56 Synchronous/Burst Read ....................................................... 57 Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) ... .........................................................................................................58 Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock) .........................................................................................................58 Figure 18. Synchronous Burst Mode Read ..................................... 59 Figure 19. 8-word Linear Burst with Wrap Around .......................... 59 Figure 20. Linear Burst with RDY Set One Cycle Before Data ....... 60 Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address............................................................................. 61 Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address .............................................................................. 61 Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh)................................................... 62 Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Fh (or Offset from 3Fh by a Multiple of 64) ..................... 62 Figure 25. Standard Handshake Burst Suspend Prior to Initial Access .........................................................................................................63 Figure 26. Standard Handshake Burst Suspend at or after Initial Ac- cess................................................................................................ 63 Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Start- ing Address 3Dh or Earlier)............................................................ 64 Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access)....................................................... 64 Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK)....................................................................... 65 Figure 30. Read Cycle for Continuous Suspend............................ 65 Asynchronous Mode Read .................................................... 66 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 31. Asynchronous Mode Read with Latched Addresses .... 67 Figure 32. Asynchronous Mode Read............................................ 67 Figure 33. Reset Timings ............................................................... 68 Erase/Program Operations ..................................................... 69 Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses ...................................................................................... 70 Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses ...................................................................................... 71 Figure 36. Synchronous Program Operation Timings: WE# Latched Addresses ...................................................................................... 72 Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses ...................................................................................... 73 Figure 38. Chip/Sector Erase Command Sequence ...................... 74 Figure 39. Accelerated Programming Timing................................. 75 Figure 40. Data# Polling Timings (During Embedded Algorithm) .. 76 Figure 41. Toggle Bit Timings (During Embedded Algorithm)........ 76 Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings 77 Figure 43. DQ2 vs. DQ6................................................................. 77 Temporary Sector Unprotect .................................................. 78 Figure 44. Temporary Sector Unprotect Timing Diagram .............. 78 Figure 45. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 79 Figure 46. Latency with Boundary Crossing .................................. 80 Figure 47. Latency with Boundary Crossing into Program/Erase Bank ............................................................... 81 Figure 48. Example of Wait States Insertion.................................. 82 Figure 49. Back-to-Back Read/Write Cycle Timings ...................... 83 Erase and Programming Performance . . . . . . . 84 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 84 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 85 VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x 9 mm Package ........................................................................ 85 VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x 8 mm Package ........................................................................ 86 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87 |
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