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AD1937XSTZ Arkusz danych(PDF) 9 Page - Analog Devices |
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AD1937XSTZ Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 30 page Preliminary Technical Data AD1935/AD1936/AD1937/AD1938/AD1939 Rev. Pr I | Page 9 of 30 FUNCTIONAL OVERVIEW ADCs There are four ADC channels in the AD193X configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48, 96 , or 192 kHz. The ADCs include on- board digital anti-aliasing filters with 79 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame (ALRCLK) and bit (ABCLK) clock. Alternatively, one of the TDM modes may be used to access up to 16 channels on a single TDM data line. The ADCs must be driven from a differential signal source for best performance. The input pins of the ADCs connect to internal switched capacitors. To isolate the external driving op amp from the “glitches” caused by the internal switched capacitors, each input pin should be isolated by using a series-connected external 100 Ω resistor together with a 1 nF capacitor connected from each input to ground. This capacitor must be of high quality; for example, ceramic NPO or polypropylene film. The differential inputs have a nominal common-mode voltage of 1.5V. The voltage at the common-mode reference pin, CM can be used to bias external op amps to buffer the input signals (see the Power Supply and Voltage Reference section). The inputs can also be AC coupled and do not need an external DC bias to CM. A digital high-pass filter can be switched in line with the ADCs under serial control to remove residual dc offsets. It has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency will scale directly with sample frequency. DACs The AD193X DAC channels are arranged as four stereo pairs giving eight analog outputs, either single-ended for minimum external components or differential for improved noise and distortion performance. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each channel has its own independently programmable attenuator, adjustable in 255 0.375 dB steps. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of the TDM modes may be used to access up to 16 channels on a single TDM data line. Each output pin has a nominal common-mode dc level of 1.5V and swings ±1.27 V for a 0 dBFS digital input signal. A single op amp third order external low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion in the case of the differential output part. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The voltage at the common-mode reference pin, CM can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section). Clock Signals The on-chip Phase Locked Loop (PLL) can be selected to use as its reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to 48kHz mode, from the MCLKI pin. The default at power-up is 256 × fS from MCLKI. In 96 kHz mode, the master clock frequency will stay at the same absolute frequency so the actual multiplication rate will be divided by 2. In 192 kHz mode, the actual multiplication rate will be divided by 4. For example, if the AD193X is programmed in 256 × fS mode, the frequency of the master clock input would be 256 × 48 kHz = 12.288 MHz. If the AD193X is then switched to 96 kHz operation (by writing to the SPI or I2C port), the frequency of the master clock should remain at 12.288 MHz, which is now 128 × fS. In 192kHz mode, this would be 64 × fS. The internal clock for the ADCs is 256 × fS for all clock modes. The internal clock for the DACs is 512 × fS (48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By default, the on-board PLL is used to generate this internal master clock from an external clock. A direct 512 × fS ( referenced to 48 kHz mode) master clock can be used for either the ADCs or DACs if selected in PLL and Clock Control Register 1. Note that it is not possible to use a direct clock for the ADCs set to 192kHz mode. It is required that the on-chip PLL be used in this mode. The PLL can be powered down in PLL and Clock Control Register 0. To ensure reliable locking when changing PLL modes or if the reference clock may be unstable at power-on, the PLL should be powered down and then powered back up when the reference clock is stable. The internal MCLK can be disabled in PLL and Clock Control Register 0 to reduce power dissipation when the AD193X is idle. The clock should be stable before it is enabled. Unless a stand- alone mode is selected (see Serial Control Port), the clock is disabled by reset and must be enabled by writing to the SPI or I2C port for normal operation. To maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms TIE (time interval error). Even at these levels, extra noise or tones may appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not being used, it is highly recommended that an independent crystal |
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