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AD9211-250EB Arkusz danych(PDF) 8 Page - Analog Devices |
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AD9211-250EB Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 21 page AD9211 Preliminary Technical Data Rev. PrA | Page 8 of 21 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD9211 56 Lead for LF-CSP TOP VIEW (Not to Scale) AVDD AVDD AVDD CML AVDD AVDD AVDD VIN- VIN+ AVDD AVDD RBIAS AVDD 34 32 41 40 39 38 33 37 36 42 31 35 30 29 PDN 11 D1- D2- D2+ D3- D3+ DRVDD DRGND D4- 13 4 5 6 7 12 8 9 2 3 14 10 1 D4+ D5- D5+ D6- D6+ D1+ Pin 0 (exposed paddle) = AGND Figure 3. Pinout Table 5. PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Description 30,32,33,34,37,38,39,41, 42,43,46 AVDD 1.8 V Analog Supply. 7, 24,47 DRVDD 1.8 V Digital Output Supply. 0 AGND1 Analog Ground. 8, 23,48 DRGND1 Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN– Analog Input—Complement. 40 CML Analog input common mode output pin 44 CLK+ Clock Input—True. 45 CLK– Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% X kohm resistor terminated to ground). 28 RESET Chip Reset ( Active high) 25 SDIO Serial port input/output pin 26 SCLK Serial port clock 27 29 CSB PWDN Serial port chip select (Active low) Chip power down 49 DCO– Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51-54 DNC Do not connect 55 D0– D0 Complement Output Bit. 56 D0+ D0 True Output Bit. 1 AGND and DRGND should be tied to a common quiet ground plane. |
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