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ISL12028IVAZ Arkusz danych(PDF) 10 Page - Intersil Corporation

Numer części ISL12028IVAZ
Szczegółowy opis  Real Time Clock/Calendar with EEPROM
Download  28 Pages
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Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12028IVAZ Arkusz danych(HTML) 10 Page - Intersil Corporation

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10
FN8233.5
October 18, 2006
NO EXTERNAL COMPENSATION RESISTORS OR
CAPACITORS ARE NEEDED OR ARE RECOMMENDED
TO BE CONNECTED TO THE X1 AND X2 PINS.
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of the second, minute, hour, day, date, month, and year. The
RTC has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that controls
24 hour or AM/PM format. When the ISL12028 powers up
after the loss of both VDD and VBAT, the clock will not
operate until at least one byte is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of the
Real Time Clock. The RTC Registers can then be read in a
Sequential Read Mode. Since the clock runs continuously
and read takes a finite amount of time, there is a possibility
that the clock could change during the course of a read
operation. In this device, the time is latched by the read
command (falling edge of the clock on the ACK bit prior to
RTC data output) into a separate latch to avoid time changes
during the read operation. The clock continuous to run.
Alarms occurring during a read are unaffected by the read
operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. RTC Register should be written ONLY with Page
Write. To avoid changing the current time by an uncompleted
write operation, write to the all 8 bytes in one write operation.
When writing the RTC registers, the new time value is
loaded into a separate buffer at the falling edge of the clock
during the Acknowledge. This new RTC value is loaded into
the RTC Register by a stop bit at the end of a valid write
sequence. An invalid write operation aborts the time update
procedure and the contents of the buffer are discarded. After
a valid write operation the RTC will reflect the newly loaded
data beginning with the next “one second” clock cycle after
the stop bit is written. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any non-volatile write sequences.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
accuracy of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
>20ppm frequency deviation translates into an accuracy of
>1 minute per month. These parameters are available from
the crystal manufacturer. Intersil’s RTC family provides on-
chip crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from -34ppm to
+80ppm when using a 12.5pF load crystal. For more detailed
information see the Application section.
Clock/Control Registers (CCR)
The Control/Clock Registers are located in an area separate
from the EEPROM array and are only accessible following a
slave byte of “1101111x” and reads or writes to addresses
[0000h:003Fh]. The clock/control memory map has memory
addresses from 0000h to 003Fh. The defined addresses are
described in the Table 2. Writing to and reading from the
undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by performing a
byte or a page write operation directly to any address in the
CCR. Prior to writing to the CCR (except the status register),
however, the WEL and RWEL bits must be set using a three
step process (See section “Writing to the Clock/Control
Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (5 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The non-
volatile portion (or the counter portion of the RTC) is updated
only if RWEL is set and only after a valid write operation and
stop bit. A sequential read or page write operation provides
access to the contents of only one section of the CCR per
operation. Access to another section requires a new
operation. A read or write can begin at any address in the
CCR.
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 (status register) supports a single
byte read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a random
read at any address in the CCR at any time. This returns the
contents of that register location. Additional registers are
read by performing a sequential read. The read instruction
latches all Clock registers into a buffer, so an update of the
X1
X2
FIGURE 11. RECOMMENDED CRYSTAL CONNECTION
ISL12028


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