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TMP105 Arkusz danych(PDF) 2 Page - Burr-Brown (TI) |
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TMP105 Arkusz danych(HTML) 2 Page - Burr-Brown (TI) |
2 / 16 page TMP105 SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 www.ti.com 2 ABSOLUTE MAXIMUM RATINGS(1) Power Supply, V+ 7.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage(2) −0.5V to 7.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Current 10mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Temperature Range −55 °C to +127°C . . . . . . . . . . . . . . . Storage Temperature Range −60 °C to +130°C . . . . . . . . . . . . . . . . . Junction Temperature (TJ max) +150 °C . . . . . . . . . . . . . . . . . . . . . . ESD Rating: Human Body Model (HBM)(3) 2000V . . . . . . . . . . . . . . . . . . . . . Charged-Device Model (CDM)(4) 500V . . . . . . . . . . . . . . . . . . . . Machine Model (MM)(5) 200V . . . . . . . . . . . . . . . . . . . . . . . . . . . . (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input voltage rating applies to all TMP105 input voltages. (3) HBM testing has been tested to TI specifications JEDEC JESD22-A114C.01. (4) CDM testing has been tested to TI specifications JEDEC EIA/JESD22-A115A. (5) MM testing has been tested to TI specifications JEDEC JESD22-C101C. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PACKAGE PART NUMBER SYMBOL Wafer chip-scale package (YZC) TMP105YZC EY (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN ASSIGNMENTS NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram. A1 B1 C1 A2 B2 C2 SDA SCL V+ GND ALERT A0 (Bump Side Down) WCSP-6 PACKAGE (TOP VIEW) |
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