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PLUS173-10 Arkusz danych(PDF) 5 Page - NXP Semiconductors |
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PLUS173-10 Arkusz danych(HTML) 5 Page - NXP Semiconductors |
5 / 8 page Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10 Programmable logic array (22 × 42 × 10) October 22, 1993 45 AC ELECTRICAL CHARACTERISTICS 0 °C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω TEST LIMITS SYMBOL PARAMETER FROM TO CONDITION MIN TYP MAX UNIT tPD Propagation Delay2 Input +/– Output +/– CL = 30pF 8 10 ns tOE Output Enable1 Input +/– Output – CL = 30pF 8 10 ns tOD Output Disable1 Input +/– Output + CL = 5pF 8 10 ns NOTES: 1. For 3-State outputs; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORM MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. 90% 10% 5ns 5ns 5ns 5ns 90% 10% +3.0V +3.0V 0V 0V tR tF Input Pulses TIMING DEFINITIONS SYMBOL PARAMETER tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE Delay between input change and when output reflects specified output level. TEST LOAD CIRCUIT TIMING DIAGRAM Test Load Circuit +5V CL R1 R2 S1 GND BZ BZ INPUTS In In BM BM OUTPUTS C2 C1 DUT NOTE: C1 and C2 are to bypass VCC to GND. VCC +3V 0V VOH VOL I, B B tPD 1.5V 1.5V 1.5V 1.5V 1.5V tOD tOE VT |
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