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M41ST84WMQ6E Arkusz danych(PDF) 9 Page - STMicroelectronics |
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M41ST84WMQ6E Arkusz danych(HTML) 9 Page - STMicroelectronics |
9 / 29 page 9/29 M41ST84W Figure 8. Bus Timing Requirements Sequence Table 2. AC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL. Symbol Parameter(1) Min Max Unit fSCL SCL Clock Frequency 0 400 kHz tBUF Time the bus must be free before a new transmission can start 1.3 µs tF SDA and SCL Fall Time 300 ns tHD:DAT (2) Data Hold Time 0 µs tHD:STA START Condition Hold Time (after this period the first clock pulse is generated) 600 ns tHIGH Clock High Period 600 ns tLOW Clock Low Period 1.3 µs tR SDA and SCL Rise Time 300 ns tSU:DAT Data Setup Time 100 ns tSU:STA START Condition Setup Time (only relevant for a repeated start condition) 600 ns tSU:STO STOP Condition Setup Time 600 ns AI00589 SDA P tSU:STO tSU:STA tHD:STA SR SCL tSU:DAT tF tHD:DAT tR tHIGH tLOW tHD:STA tBUF S P |
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