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ZL50030 Arkusz danych(PDF) 6 Page - Zarlink Semiconductor Inc |
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ZL50030 Arkusz danych(HTML) 6 Page - Zarlink Semiconductor Inc |
6 / 73 page ZL50030 Data Sheet 6 Zarlink Semiconductor Inc. A15, A16, B12, B13 LSTio4 - 7 Group 1 Local Serial Bi-directional Streams 4 - 7 (5 V Tolerant I/Os). In 2 Mbps, 4 Mbps or 8 Mbps mode, these pins accept or output (selectable on a per channel basis) data rates of 2.048, 4.096 or 8.192 Mbps with 32, 64 or 128 channels per stream respectively. B14, D16, D15, B15 LSTio8 - 11 Group 2 Local Serial Bi-directional Streams 8 - 11 (5 V Tolerant I/Os). In 2 Mbps, 4 Mbps or 8 Mbps mode, these pins accepts or output (selectable on a per channel basis) data rates of 2.048, 4.096 or 8.192 Mbps with 32, 64 or 128 channels per stream respectively. B16, C14, C15, C16 LSTio12 - 15 Group 3 Local Serial Bi-directional Streams 12 - 15 (5 V Tolerant I/Os). In 2 Mbps, 4 Mbps or 8 Mbps mode, these pins accept or output (selectable on a per channel basis) data rates of 2.048, 4.096 or 8.192 Mbps with 32, 64 or 128 channels per stream respectively. H16 ODE Output Drive Enable (5 V Tolerant Input). When this pin is low, LSTio0-15, BSTio0-31, C1M5o, C32/64o, ST_CKo0, ST_CKo1, ST_FPo0 and ST_FPo1 outputs are all in high-impedance state. When ODE is high all of the aforementioned pins are active. P15 C20i Master Clock (5 V Tolerant Input). This pin accepts a 20.000 MHz clock. K15 C8_A_io Clock A (5 V Tolerant I/O). This is an 8.192 MHz clock with 50% duty cycle. K16 FRAME_A_io Frame Reference A (5 V Tolerant I/O). This is a 122ns wide, negative pulse, with 125us period. G16 A_Active A Clock Active Indicator (5 V Tolerant Output): This pin indicates whether the C8_A_io and the FRAME_A_io pins are inputs or outputs. When Bit 13 of the DOM1 register is low, this pin drives low and the C8_A_io and FRAME_A_io output drivers are disabled. When Bit 13 of the DOM1 register is high, this pin drives high and the C8_A_io and FRAME_A_io output drivers are enabled. L15 C8_B_io Clock B (5 V Tolerant I/O). This is an 8.192 MHz clock with 50% duty cycle. L16 FRAME_B_io Frame Reference B (5 V Tolerant I/O). This is a 122 ns wide, negative pulse, with 125us period. F16 B_Active B Clock Active Indicator (5 V Tolerant Output): This pin indicates whether the C8_B_io and the FRAME_B_io pins are inputs or outputs. When Bit 14 of the DOM1 register is low, this pin drives low and the C8_B_io and FRAME_B_io output drivers are disabled. When Bit 14 of the DOM1 register is high, this pins drives high and the C8_B_io and FRAME_B_io output drivers are enabled. E16 FAIL_A A Failure (Output). When the C8_A_io or the FRAME_A_io signal fails, this signal goes to high. J16 FAIL_B B Failure (Output). When the C8_B_io or the FRAME_B_io signal fails, this signal goes to high. M15 CTREF1 CT-Bus Reference 1 (5 V Tolerant Input). This pin accepts 8 kHz, 1.544 MHz or 2.048 MHz network timing reference. Pin Description (continued) PBGA Ball Number Name Description |
Podobny numer części - ZL50030_06 |
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Podobny opis - ZL50030_06 |
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