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STP16CP05XTR Arkusz danych(PDF) 10 Page - STMicroelectronics |
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STP16CP05XTR Arkusz danych(HTML) 10 Page - STMicroelectronics |
10 / 26 page Timing diagrams STP16CP05 10/26 5 Timing diagrams Note: OUT0 to OUT15 = ON when Dn = H; OUT0 to OUT15 = OFF when Dn = L. Figure 7. Timing diagram Note: The latches circuit holds data when the LE terminal is Low. 1 When LE terminal is at High level, latch circuit hold the data it passes from the input to the output. 2 When OE terminal is at Low level, output terminals OUT0 to OUT15 respond to the data, either ON or OFF. 3 When OE terminal is at High level, it switches off all the data on the output terminal. Table 8. Truth Table CLOCK LE /OE SERIAL- IN OUT0 ............. OUT7 ................ OUT15 SDO H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 L L Dn + 1 No Change Dn - 14 H L Dn + 2 Dn - 2 ..... Dn - 5 ..... Dn -13 Dn - 13 X L Dn + 3 Dn - 2 ..... Dn - 5 ..... Dn -13 Dn - 13 X L Dn + 3 ON Dn - 13 |
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