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MC10EP32DR2G Arkusz danych(PDF) 1 Page - ON Semiconductor

Numer części MC10EP32DR2G
Szczegółowy opis  3.3V / 5V ECL 첨2 Divider
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© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 10
1
Publication Order Number:
MC10EP32/D
MC10EP32, MC100EP32
3.3V / 5VECL B2 Divider
Description
The MC10/100EP32 is an integrated
B2 divider with differential
CLK inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power−up, the internal flip−flops will attain a random state; the
reset allows for the synchronization of multiple EP32’s in a system.
The 100 Series contains temperature compensation.
Features
350 ps Typical Propagation Delay
Maximum Frequency > 4 GHz Typical (Figure 3)
PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
Pb−Free Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
H
= MC10
K
= MC100
5P
= MC10
3K
= MC100
M
= Date Code
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
ALYWG
G
HP32
ALYWG
G
KP32
1
8
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
8
HEP32
ALYW
G
1
8
KEP32
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
14
14
(Note: Microdot may be in either location)


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