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MC74ACT139DR2 Arkusz danych(PDF) 2 Page - ON Semiconductor |
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MC74ACT139DR2 Arkusz danych(HTML) 2 Page - ON Semiconductor |
2 / 11 page MC74AC139, MC74ACT139 http://onsemi.com 2 EA0 A1 O0 O1 O2 O3 DECODER a Figure 2. Logic Symbol E A0 A1 O0 O1 O2 O3 DECODER b Ea A0a A1a Eb A0b A1b 00a 01a 02a 03a 00b 01b 02b 03b NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram FUNCTIONAL DESCRIPTION The MC74AC139/74ACT139 is a high−speed dual 1−of−4 decoder/demultiplexer. The device has two independent decoders, each of which accepts two binary weighted inputs (A0−A1) and provides four mutually exclusive active−LOW outputs (O0−O3). Each decoder has an active−LOW enable (E). When E is HIGH all outputs are forced HIGH. The enable can be used as the data input for a 4−output demultiplexer application. Each half of the MC74AC139/74ACT139 generates all four minterms of two variables. These four minterms are useful in some applications, replacing multiple gate functions as shown in Figure 4, and thereby reducing the number of packages required in a logic network. E A0 A1 E A0 A1 E A0 A1 E A0 A1 E A0 A1 E A0 A1 E A0 A1 E A0 A1 O0 O0 O1 O1 O2 O2 O3 O3 Figure 4. Gate Functions (Each Half) |
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