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MC100EP809 Arkusz danych(PDF) 5 Page - ON Semiconductor |
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MC100EP809 Arkusz danych(HTML) 5 Page - ON Semiconductor |
5 / 9 page MC100EP809 http://onsemi.com 5 Table 7. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V Symbol Characteristic 0°C 25°C 85°C Unit Min Typ Max Min Typ Max Min Typ Max VOH Output HIGH Voltage (Note 3) 1.0 1.2 1.0 1.2 1.0 1.2 V VOL Output LOW Voltage (Note 3) 0.1 0.4 0.1 0.4 0.1 0.4 V VIH Input HIGH Voltage (Figure 5) VX + 0.1 1.6 VX + 0.1 1.6 VX + 0.1 1.6 V VIL Input LOW Voltage (Figure 5) −0.3 VX − 0.1 −0.3 VX − 0.1 −0.3 VX − 0.1 V VX HSTL Input Crossover Voltage 0.68 − 0.9 0.68 − 0.9 0.68 − 0.9 V IIH Input HIGH Current −150 150 −150 150 −150 150 mA IIL Input LOW Current −300 300 −300 300 −300 300 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) HSTL_CLK/HSTL_CLK 0.6 VCCI − 1.2 0.6 VCCI − 1.2 0.6 VCCI − 1.2 V V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. All outputs loaded with 50 W to GND (Figure 6). 4. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 5) Symbol Characteristic 0°C 25°C 85°C Unit Min Typ Max Min Typ Max Min Typ Max VOpp Differential Output Voltage fout < 100 MHz (Figure 3) fout < 500 MHz fout < 750 MHz 600 600 450 850 750 575 600 600 450 850 750 575 600 600 450 850 750 575 mV mV tPLH tPHL Propagation Delay (Differential Configura- tion) LVPECL_CLK to Q HSTL_CLK to Q 680 690 800 830 930 990 700 700 820 850 950 1000 780 790 920 950 1070 1110 ps ps tskew Within−Device Skew (Note 6) Device−to−Device Skew (Note 7) 15 100 50 200 15 100 50 200 15 100 50 200 ps ps tJITTER Random Clock Jitter (Figure 3) (RMS) 1.4 3.0 1.4 3.0 1.4 3.0 ps VPP Input Swing (Differential Configuration) (Note 8) (Figure 4) LVPECL HSTL 200 200 200 200 200 200 mV mV tS OE Set Up Time (Note 9) 0.5 0.5 0.5 ns tH OE Hold Time 0.5 0.5 0.5 ns tr/tf Output Rise/Fall Time (20% − 80%) 350 600 350 450 600 350 600 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to GND (Figure 6). 6. Skew is measured between outputs under identical transitions and conditions on any one device. 7. Device−to−Device skew for identical transitions and conditions. 8. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein. 9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (Figure 8). |
Podobny numer części - MC100EP809_06 |
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Podobny opis - MC100EP809_06 |
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