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MC100LVEL01D Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC100LVEL01D Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 3 1 Publication Order Number: MC100LVEL01/D MC100LVEL01 3.3VECL 4−Input OR/NOR Description The MC100LVEL01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in AC performance. Features • 370 ps Propagation Delay • High Bandwidth Output Transitions • ESD Protection: >2 kV Human Body Model, >200 V Machine Model • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V • Internal Input Pulldown Resistors • Q Output will Default LOW with All Inputs Open or at VEE • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index 28 to 34 • Transistor Count = 83 devices • Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAMS* KV01 ALYWG G SOIC−8 D SUFFIX CASE 751 1 8 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION http://onsemi.com KVL01 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) |
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