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CD3206BB Arkusz danych(PDF) 3 Page - NXP Semiconductors |
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CD3206BB Arkusz danych(HTML) 3 Page - NXP Semiconductors |
3 / 18 page Philips Semiconductors Product specification FB2031 9-bit latched/registered/pass-thru Futurebus+ transceiver 1995 May 25 3 DESCRIPTION The FB2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FB2031 is intended to provide the electrical interface to a high performance wired-OR bus. The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A “00” configures latches in both directions. A “10” configures thru mode in both directions. A “01” configures register mode in both directions. A “11” configures register mode in the A-to-B direction and latch mode in the B-to-A direction. When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output. The 3-State A port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pullup voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to “Backplane Transceiver Logic” (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The “VOH” clamp reduces inductive ringing effects during a Low-to-High transition. The “VOH” clamp is always active. The other clamp, the “trapped reflection” clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature. PACKAGE THERMAL CHARACTERISTICS PARAMETER CONDITION 52-PIN PLASTIC QFP θja Still air 80 °C/W θja 300 Linear feet per minute air flow 58 °C/W θjc Thermally mounted on one side to heat sink 20 °C/W PIN DESCRIPTION SYMBOL PIN NUMBER TYPE NAME AND FUNCTION A0 – A8 50, 52, 2, 4, 6, 8, 10, 12, 14 I/O BiCMOS data inputs/3-State outputs (TTL) B0 – B8 40, 38, 36, 34, 32, 30, 28, 26, 24 I/O Data inputs/Open Collector outputs, High current drive (BTL) OEB0 46 Input Enables the B outputs when High OEB1 45 Input Enables the B outputs when Low OEA 47 Input Enables the A outputs when High BUS GND 25, 27, 29, 31, 33, 35, 37, 39, 41 GND Bus ground (0V) LOGIC GND 51, 1, 3, 5, 7, 9, 11, 13 GND Logic ground (0V) VCC 23, 43, 49 Power Positive supply voltage BIAS V 48 Power Live insertion pre-bias pin BG VCC 17 Power Band Gap threshold voltage reference BG GND 19 GND Band Gap threshold voltage reference ground SEL0 20 Input Mode select SEL1 15 Input Mode select LCAB 18 Input A to B clock/latch enable (transparent latch when Low) LCBA 16 Input B to A clock/latch enable (transparent latch when Low) TMS 42 Input Test Mode Select (optional, if not implemented then no connect) TCK 44 Input Test Clock (optional, if not implemented then no connect) TDI 22 Input Test Data In (optional, if not implemented then no connect) TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI) |
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