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LF298 Arkusz danych(PDF) 1 Page - NXP Semiconductors

Numer części LF298
Szczegółowy opis  Sample-and-hold amplifiers
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

LF298 Arkusz danych(HTML) 1 Page - NXP Semiconductors

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Philips Semiconductors Linear Products
Product specification
LF198/LF298/LF398
Sample-and-hold amplifiers
879
August 31, 1994
853-0135 13721
DESCRIPTION
The LF198/LF298/LF398 are monolithic sample-and-hold circuits
which utilize high-voltage ion-implant JFET technology to obtain
ultra-high DC accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6
µs to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF198 to be included inside the feedback loop of 1MHz op amps
without having stability problems. Input impedance of 1010
Ω allows
high source impedances to be used without degrading accuracy.
P-channel junction FETs are combined with bipolar devices in the
output amplifier to give droop rates as low as 5mV/min with a 1
µF
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.
Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is
1.4V. The LF198/LF298/LF398 will operate from
±5V to ±18V
supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and
14-pin plastic SO packages.
FEATURES
Operates from ±5V to ±18V supplies
Less than 10µs acquisition time
TTL, PMOS, CMOS compatible logic input
0.5mV typical hold step at CH=0.01µF
Low input offset
0.002% gain accuracy
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
PIN CONFIGURATIONS
FE, N Packages
D1 Package
NOTE:
1. SO and non-standard pinouts.
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
14
13
12
11
10
9
V+
OFFSET VOLTAGE
INPUT
V–
NC
V+
OUTPUT
LOGIC
INPUT
V–
LOGIC REF
NC
NC
NC
NC
NC
LOGIC
LOGIC REFERENCE
OUTPUT
VOS Adj
Ch
Ch
APPLICATION
The LF198/LF298/LF398 are ideally suited for a wide variety of
sample-and-hold applications, including data acquisition,
analog-to-digital conversion, synchronous demodulation, and
automatic test setup
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
8-Pin Ceramic Dual In-Line Package (CERDIP)
-55
°C to +125°C
LF198FE
0580A
14-Pin Plastic Small Outline (SO) Package
0 to +70
°C
LF398D
0175D
8-Pin Ceramic Dual In-Line Package (CERDIP)
0 to +70
°C
LF398FE
0580A
8-Pin Plastic Dual In-Line Package (DIP)
0 to +70
°C
LF398N
0404B
8-Pin Ceramic Dual In-Line Package (CERDIP)
-25
°C to +85°C
LF298FE
0580A
8-Pin Plastic Dual In-Line Package (DIP)
-25
°C to +85°C
LF298N
0404B


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