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FIN24ACMLX Arkusz danych(PDF) 7 Page - Fairchild Semiconductor |
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FIN24ACMLX Arkusz danych(HTML) 7 Page - Fairchild Semiconductor |
7 / 25 page © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN24AC Rev. 1.0.3 7 Serializer Operation Mode (Continued) A third method of serialization can be accomplished with a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up, the device is configured to accept a serialization clock from CKSI. If a CKREF is received, this device enables the CKREF serialization mode. The device remains in this mode even if CKREF is stopped. To re-enable this mode, the device must be powered down and powered back up with a “logic 0” on CKREF. Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) WORD n-1 WORD n-1 WORD n No Data No Data DP[1:24] DSO CKS0 CKSI STROBE b1 b2 b3 b1 b2 b3 b4 b5 b6 b7 b22 b23 b24 b25 b26 WORD n+1 WORD n Serializer Operation: (Figure 6), DIRI = 1, No CKREF |
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