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FIN224ACGFX Arkusz danych(PDF) 10 Page - Fairchild Semiconductor |
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FIN224ACGFX Arkusz danych(HTML) 10 Page - Fairchild Semiconductor |
10 / 23 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN224AC Rev.1.1.2 10 Application Mode Diagrams Figure 12. FIN224AC RGB Figure 13. FIN224AC Microcontroller Flex Circuit Design Guidelines The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB: ■ Keep all four differential wires the same length. ■ Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires. ■ Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. ■ Do not place test points on differential serial wires. ■ Use differential serial wires a minimum of 2cm away from the antenna. U20 2.8V 1.8V VDDP 2.8V 2.8V LCD14_M LCD10_M LCD2_M LCD6_M LCD8_M LCD12_M LCD4_M LCD1_M LCD15_M LCD5_M LCD11_M LCD9_M LCD7_M LCD13_M PIXCLK_M LCD3_M GPIO_MODE LCD_ENABLE_M LCD16_M LCD17_M LCD0_S LCD0_M LCD_HSYNC_M LCD_VSYNC_M LCD1_S LCD2_S LCD3_S LCD4_S LCD5_S LCD6_S LCD7_S LCD8_S LCD9_S LCD10_S LCD11_S LCD12_S LCD13_S LCD14_S LCD15_S LCD16_S LCD17_S LCD_HSYNC_S LCD_VSYNC_S PIXCLK_S µSerDes Serializer LCD Controller Out LCD Display In Assumptions: 1) 18-bit Unidirectional RGB Application 2) Mode 2 Operation (5Mhz to 15Mhz CKREF) µSerDes DeSerializer 3) VDDP= (1.65V to 3.6V) FIN224AC U22 DP9 A1 DP7 A2 DP5 A3 DP3 A4 DP1 A5 CKREF A6 DP11 B1 DP10 B2 DP6 B3 DP2 B4 STROBE B5 DIRO B6 CKP C1 DP12 C2 DP8 C3 DP4 C4 CKSO+ C5 CKSO- C6 DP13 D1 DP14 D2 VDDP D3 DSO-/DSI+ D5 DSO+/DSI- D6 CKSI- E6 CKSI+ E5 VDDS E4 DP16 E2 DP15 E1 DIRI F6 S1 F5 VDDA F4 DP21 F3 DP18 F2 DP17 F1 S2 J6 DP24 J5 DP23 J4 DP22 J3 DP20 J2 DP19 J1 TP6 1nF C10 1nF 1nF C6 1nF .01µF C12 FIN224AC DP9 A1 DP7 A2 DP5 A3 DP3 A4 DP1 A5 CKREF A6 DP11 B1 DP10 B2 DP6 B3 DP2 B4 STROBE B5 DIRO B6 CKP C1 DP12 C2 DP8 C3 DP4 C4 CKSO+ C5 CKSO- C6 DP13 D1 DP14 D2 VDDP D3 DSO-/DSI+ D5 DSO+/DSI- D6 CKSI- E6 CKSI+ E5 VDDS E4 DP16 E2 DP15 E1 DIRI F6 S2 F5 VDDA F4 DP21 F3 DP18 F2 DP17 F1 S1 J6 DP24 J5 DP23 J4 DP22 J3 DP20 J2 DP19 J1 TP5 .01µF C3 C11 2.2µF LCD_ENABLE_S 2.8V 1.8V VDDP 2.8V 2.8V LCD14_M LCD10_M LCD2_M LCD6_M LCD8_M LCD12_M LCD4_M LCD1_M LCD15_M LCD5_M LCD11_M LCD9_M LCD7_M LCD13_M REFCLK LCD3_M GPIO_MODE LCD_/WRITE_ENABLE_M LCD16_M LCD17_M LCD0_S LCD0_M LCD_ADDRESS_M LCD_/CS_M LCD1_S LCD2_S LCD3_S LCD4_S LCD5_S LCD6_S LCD7_S LCD8_S LCD9_S LCD10_S LCD11_S LCD12_S LCD13_S LCD14_S LCD15_S LCD16_S LCD17_S LCD_ADDRESS_S LCD_/CS_S LCD_/WRITE_ENABLE_S µSerDes Serializer LCD Controller Out LCD Display In Assumptions: 1) 18-bit Unidirectional µController Application 2) Mode 3 Operation (10 Mhz to 20Mhz CKREF) µSerDes DeSerializer 3) VDDP= (1.65V to 3.6V) 4) REFCLK is a continously running clock with a frequency greater than /WRITE_ENABLE. U23 FIN224AC U23 FIN224AC DP9 A1 DP7 A2 DP5 A3 DP3 A4 DP1 A5 CKREF A6 DP11 B1 DP10 B2 DP6 B3 DP2 B4 STROBE B5 DIRO B6 CKP C1 DP12 C2 DP8 C3 DP4 C4 CKSO+ C5 CKSO- C6 DP13 D1 DP14 D2 VDDP D3 DSO-/DSI+ D5 DSO+/DSI- D6 CKSI- E6 CKSI+ E5 VDDS E4 DP16 E2 DP15 E1 DIRI F6 S2 F5 VDDA F4 DP21 F3 DP18 F2 DP17 F1 S1 J6 DP24 J5 DP23 J4 DP22 J3 DP20 J2 DP19 J1 TP2 TP2 1nF C7 1nF C7 1nF C5 1nF C5 .01uF C9 .01µF C9 TP1 TP1 U21 FIN224AC U21 FIN224AC DP9 A1 DP7 A2 DP5 A3 DP3 A4 DP1 A5 CKREF A6 DP11 B1 DP10 B2 DP6 B3 DP2 B4 STROBE B5 DIRO B6 CKP C1 DP12 C2 DP8 C3 DP4 C4 CKSO+ C5 CKSO- C6 DP13 D1 DP14 D2 VDDP D3 DSO-/DSI+ D5 DSO+/DSI- D6 CKSI- E6 CKSI+ E5 VDDS E4 DP16 E2 DP15 E1 DIRI F6 S2 F5 VDDA F4 DP21 F3 DP18 F2 DP17 F1 S1 J6 DP24 J5 DP23 J4 DP22 J3 DP20 J2 DP19 J1 TP3 TP3 .01uF C2 .01µF C2 C8 2.2uF C8 2.2µF |
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Podobny opis - FIN224ACGFX |
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