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AD9211-200EBZ Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD9211-200EBZ
Szczegółowy opis  10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9211-200EBZ Arkusz danych(HTML) 11 Page - Analog Devices

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AD9211
Rev. 0 | Page 11 of 28
DNC = DO NOT CONNECT
PIN 1
INDICATOR
1
D2/D7–
2
D2/D7+
3
D3/D8–
4
D3/D8+
5
(MSB) D4/D9–
6
(MSB) D4/D9+
7
DRVDD
8
DRGND
9
OR–
10
OR+
11
DNC
12
DNC
13
DNC
14
DNC
35 VIN+
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
AD9211
Figure 5. AD9211 Double Data Rate Pin Configuration
Table 8. Double Data Rate Mode Pin Function Descriptions
Pin No.
Mnemonic
Description
30, 32 to 34, 37 to 39,
41 to 43, 46
AVDD
1.8 V Analog Supply.
7, 24, 47
DRVDD
1.8 V Digital Output Supply.
0
AGND1
Analog Ground.
8, 23, 48
DRGND1
Digital Output Ground.
35
VIN+
Analog Input—True.
36
VIN−
Analog Input—Complement.
40
CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44
CLK+
Clock Input—True.
45
CLK−
Clock Input—Complement.
31
RBIAS
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
28
RESET
CMOS-Compatible Chip Reset (Active Low).
25
SDIO/DCS
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
26
SCLK/DFS
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27
CSB
Serial Port Chip Select (Active Low).
29
PWDN
Chip Power-Down.
49
DCO−
Data Clock Output—Complement.
50
DCO+
Data Clock Output—True.
53
D0/D5−
D1/D7 Complement Output Bit (LSB).
54
D0/D5+
D1/D7 True Output Bit (LSB).
55
D1/D6−
D2/D8 Complement Output Bit.
56
D1/D6+
D2/D8 True Output Bit.
1
D2/D7−
D3/D9 Complement Output Bit.
2
D2/D7+
D3/D9 True Output Bit.
3
D3/D8−
D4/D10 Complement Output Bit.
4
D3/D8+
D4/D10 True Output Bit.
5
D4/D9−
D5/D11 Complement Output Bit (MSB).
6
D4/D9+
D5/D11 True Output Bit (MSB).


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