Philips Semiconductors

Product specification

N-channel enhancement mode

PHN70308

TrenchMOS transistor array

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

T

-

25

V

V

DGR

Drain-gate voltage

R

-25

V

V

GS

Gate-source voltage

-

± 20

V

I

D

Peak drain current per device

T

1

(continuous operation)

spindle FETs;

δ = 33.3%

-

5

A

Isolation FET (dc)

-

5

A

I

DM

Peak current per device (pulse

spindle FETs

-

20

A

peak value)

isolation FET

-

20

A

P

tot

Power dissipation per device

2

T

spindle FETs;

δ = 33.3%

-

1.13

W

isolation FET (dc)

-

1.275

W

P

tot

Total power dissipation in normal

T

-

8

W

operation

2

spindle FETs;

δ = 33.3%

isolation FET (dc)

T

Storage & operating temperature

- 55

150

˚C

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-sp

Thermal resistance junction to

isolation FET

20

-

K/W

solder point

spindle FET

43

-

K/W

R

th j-a

Thermal resistance junction to

device soldered to FR4 board,

ambient

minimum footprint.

isolation FET

85

-

K/W

spindle FET

100

-

K/W

1 T

2 In normal operation, the isolation FET conducts continuously whilst each of the spindle FETs conducts for 33.3%

of the time. The dissipation in the isolation transistor is given by:-

The dissipation in each of the spindle transistors is given by:-

The total dissipation under these conditions is given by:-

With the motor being driven at 5 A and assuming T

Switching losses are assumed to be negligible.

P

DS

(ON)(isolationFET)

P

DS

(ON)(spindleFET)

P

P

May 1999

2

Rev 1.000