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ST16C2552IJ44 Arkusz danych(PDF) 7 Page - Exar Corporation

Numer części ST16C2552IJ44
Szczegółowy opis  2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
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ST16C2552
7
REV. 4.2.1
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
2.0
FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2552 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3.
.
2.2
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see the Table 11). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.3
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
in Table 1.
FIGURE 3.
ST16C2552 DATA BUS INTERCONNECTIONS
TABLE 1: CHANNEL A AND B SELECT
CS#
CHSEL
FUNCTION
1
X
UART de-selected
0
1
Channel A selected
0
0
Channel B selected
VCC
VCC
(OP2A#)
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
(OP2B#)
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CS#
UART_CHSEL
IOR#
IOW #
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CS#
CHSEL
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW #
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
(RXRDYA#)
TXRDYA#
(RXRDYA#)
TXRDYA#
(RXRDYB#)
TXRDYB#
(RXRDYB#)
TXRDYB#
UART_RESET
RESET
Serial Interface of
RS-232, RS-485
Serial Interface of
RS-232, RS-485
2750int
(BAUDOUTB#)
(BAUDOUTA#)
Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B
when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'.


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