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TDA10045 Arkusz danych(PDF) 6 Page - NXP Semiconductors |
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TDA10045 Arkusz danych(HTML) 6 Page - NXP Semiconductors |
6 / 20 page 2001 Nov 08 6 Philips Semiconductors Product specification DVB-T channel receiver TDA10045H FFT_WIN 30 I/O output or input signal indicating the start of the active data; equals 1 during complex sample 0 of the active FFT block; can be used to synchronize 2 chips VDDD33 31 − digital supply voltage for the pads (3.3 V typ.) VSSD 32 − digital ground supply (0 V) SACLK 33 O sampling frequency output; this output clock can be fed to an external (10-bit) ADC as a sampling clock; SACLK can also provide twice the sampling clock FI[9:5] 34 to 38 I/O input data from an external ADC, FI must be tied to ground when unused, positive notation (from 0 to 1023) or twos complement notation (from −512 to +511). In internal ADC mode, these outputs can be used to monitor extra demodulator output signals (constellation or frequency response). VDDD18 39 − digital supply voltage for the core (1.8 V typ.) VSSD 40 − digital ground supply (0 V) FI[4:0] 41 to 45 IO input data from an external ADC, FI must be tied to ground when unused, positive notation (from 0 to 1023) or twos complement notation (from −512 to +511). In internal ADC mode, these outputs can be used to monitor extra demodulator output signals (constellation or frequency response). VDDD50 46 − digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if 5 V tolerant I/O is not required VSSD 47 − digital ground supply (0 V) IT 48 OD(1) interrupt line; this output interrupt line can be configured by the I2C-bus interface. This pin is an open-drain output and therefore requires an external pull-up resistor (to VDDD33 or VDDD50). FEL 49 OD(1) front-end lock; FEL is an open-drain output and therefore requires an external pull-up resistor (to VDDD33 or VDDD50) n.c. 50 − not connected n.c. 51 − not connected TRSTN 52 I(2) asynchronous reset signal for boundary scan; connected to GND if not used TMS 53 I(2) mode programming signal for boundary scan; connected to GND if not used TDI 54 I(2) input port for boundary scan; connected to GND if not used TCK 55 I(2) clock signal for boundary scan; connected to GND if not used) TDO 56 O output port for boundary scan; not connected if not used VDDD18 57 − digital supply voltage for the core (1.8 V typ.) VSSD 58 − digital ground supply (0 V) DS_SPARE2 59 O spare delta-sigma output; managed by the DSP or by an I2C-bus register to generate an analog level (after a RC low-pass filter) DS_SPARE1 60 O spare delta-sigma output; managed by the DSP to handle a low frequency DAC (automatic first stage tuner AGC measurement or 2nd AGC loop control as examples) VDDD33 61 − digital supply voltage for the pads (3.3 V typ.) VSSD 62 − digital ground supply (0 V) UNCOR 63 O RS error flag, active HIGH on one RS packet if the RS decoder fails to correct the errors PSYNC 64 O pulse synchro; this output signal goes HIGH on a rising edge of OCLK when a synchro byte is provided, then goes LOW until the next synchro byte SYMBOL PIN TYPE DESCRIPTION |
Podobny numer części - TDA10045 |
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Podobny opis - TDA10045 |
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